1) Field of the Invention
The present invention relates to a method for fabricating semiconductor devices, and more particularly to a method for fabricating capacitors with a structure having hemispherical grains, which is capable of forming a large amount of silicon-dangling bonds while suppressing the growth of a natural oxide film on the surface of a lower electrode layer, thereby achieving an improvement in the growth of hemispherical grains.
2) Description of the Related Art
In a semiconductor memory device, such as a dynamic random access memory (DRAM), including a plurality of memory cells each consisting of one access transistor and one storage capacitor, cell capacitance is important for an improvement in cell memory characteristics in that it serves to improve the read-out ability of the memory device while reducing the soft error rate (SER). However, the recent high integration trend of semiconductor devices inevitably involves a reduction in the cell area per cell, thereby resulting in a reduction in the area occupied by the capacitor. For this reason, it is essentially required to achieve an increase in the capacitance per cell area, in addition to an increase in the integration degree.
Generally, capacitance is proportional to how much area is shared by lower and upper electrode layers. A number of efforts have continuously been made to increase the surface area of the lower electrode layer in a limited space. Most of such efforts are concerned with lower electrode layer structures. By virtue of such efforts, capacitors have been developed from planar capacitor structures, which were initially proposed, to three-dimensional capacitor structures such as those of stacked capacitors or trenched capacitors. However, attempts to increase capacitance by an improved lower electrode layer structure as mentioned above encounter problems such as a limited design rule and complicated fabrication processes.
To this end, proposals have been made to utilize physical properties of the lower electrode layer, thereby achieving an increase in capacitance. Of these proposals, one is disclosed in U.S. Pat. No. 5,385,863, wherein hemispherical grains (HSG) are formed on the surface of a lower electrode layer, thereby increasing the surface area of the lower electrode layer. In accordance with this method, an amorphous silicon layer is formed over a wafer using a low pressure chemical vapor deposition (LPCVD) process. Phosphorous (P) ions are then implanted in the amorphous silicon layer. Subsequently, the surface of the amorphous silicon layer is cleaned, thereby removing a natural oxide film existing thereon. The resulting wafer is then loaded in a chamber defined in an ultra-high vacuum CVD device. The chamber is maintained at an ultra-high vacuum of 10.sup.-9 Torr. In the chamber, the wafer is heated to a desired temperature ranging from 550.degree. C. to 620.degree. C. Under this condition, source gas such as silane (SiH.sub.4) or disilane (Si.sub.2 H.sub.6) is supplied into the chamber, so that crystal nucleuses are formed on the amorphous silicon layer. This technique is generally called a "crystal seeding process". After the formation of the crystal nucleuses, the resulting wafer is subjected to a high vacuum annealing in an N.sub.2 atmosphere. By this annealing, silicon atoms migrate from Si-dangling bonds existing on the surface of the amorphous silicon layer to the crystal nucleuses, so that those crystal nucleuses are grown into hemispherical grains. Consequently, the amorphous silicon layer is transformed into a polysilicon layer having an irregular surface.
Generally, Si--Si bond energy in an amorphous silicon layer is 1.58 eV whereas Si--Si bond energy in a single-crystalline silicon layer is 2.4 eV. For this reason, where the growth of hemispherical grains is carried out at a high temperature, a rapid crystallization of amorphous silicon occurs, thereby forming grain boundaries interfering with a migration of silicon atoms. Therefore, the growth temperature of hemispherical grains should be in a range of 550 to 620.degree. C. so that the migration of silicon atoms occurs prior to the crystallization of amorphous silicon.
In accordance with the above-mentioned conventional hemispherical grain formation method, however, a natural oxide film is formed on the surface of the amorphous silicon layer of a wafer when the amorphous silicon layer is exposed to the atmosphere in the process of feeding the wafer to an ultra-high vacuum CVD device after cleaning the wafer. Such a natural oxide film serves to suppress migration of silicon atoms from the surface of the amorphous silicon layer during the growth of hemispherical grains. As a result, the crystal nucleuses on the amorphous silicon layer can not be grown into hemispherical grains.
Meanwhile, in the process of growing hemispherical grains, a large amount of Si-dangling bonds should exist on the surface of the amorphous silicon layer in order to achieve an active migration of silicon atoms to the crystal nucleuses on the amorphous silicon layer. Accordingly, it is necessary to remove Si-dangling bonds existing on the surface of the amorphous silicon layer prior to the formation of hemispherical grains, in order to avoid the formation of natural oxide films on the amorphous silicon layer whereas a large amount of Si-dangling bonds should exist on the surface of the amorphous silicon layer during the process of forming hemispherical grains.